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Algorithm Design in the Era of Reconfigurable Computing
Posted Wed June 28, 2006 @03:04PM
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Announcements Accelogic will present Algorithm Design in the Era of Reconfigurable Computing from July 12-14, 2006 in Dayton, Ohio.

Reconfigurable computing algorithms implemented in FPGAs are 10x to 1,000x faster than traditional parallel algorithms. Many high-performance computing applications are turning to FPGAs and reconfigurable computing to squeeze performance for their biggest computational challenges.


Sponsor CFD Review

Although the algorithm implementation cycle in reconfigurable computing is similar in principle to that of a traditional software solution (code program, debug, compile, test), mastering the art of reconfigurable computing requires a paradigm shift in the thought process of the algorithm developer. Under this new paradigm, you free yourself from the limitations imposed by an instruction-based machine architecture (known in the literature as the "von Neumann or software bottleneck"), and open the door to a liberated world, full of opportunities for the discovery of new and groundbreaking algorithms, in which you can manipulate the machine architecture to best solve your problem.

The aim of this course is to disseminate this cutting edge technology among the scientific, research and industry professionals that can benefit directly from it.

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CFDOIL2006 - CFD Workshop for the Oil Industry | New Preprocessing Releases Improve CAD Interoperability and Enhance Mesh Generation  >

 

 
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